CMOS image sensors generally require two signals to read from each pixel in the image: (a) the pixel offset level (N); and (b) the pixel signal level (NS). The pixel offset level N does not contain image information but is the offset level of each pixel. The pixel signal level NS carries the image information relative to the offset N. Both N and NS are read for each pixel because the pixel offset N depends on parameters, such as charge feed-through during the pixel reset, which vary from pixel to pixel. These two signals are conventionally read from each pixel sequentially and stored in capacitors placed at the end of each column of pixels. The complete set of all the column capacitors is called line memory because it stores the information for a complete line of the image.
The image readout process of a conventional CMOS sensor based on passive column circuits is as follows:
(a) A line in the image is selected and corresponding small buffers inside each pixel are turned on;
(b) Each pixel buffer drives a capacitor placed at the column to store its pixel offset N;
(c) The column capacitor storing the pixel offset N is switched out and a new capacitor is switched in;
(d) The pixel buffers drive the new capacitors to store its pixel signal NS;
(e) The two lines of capacitors now store respective pixel offset N and pixel signal NS for the active image line;
(f) All pixel offset N capacitors are connected through a switch to a line called the N bus. Similarly, all pixel signal NS capacitors connect to an NS bus;
(g) The N and NS buses are reset to a reference level called Vref;
(h) The N capacitor switch of the first column is turned on and its charge is shared with the N bus. The same happens for the NS capacitor and its bus;
(i) A differential amplifier subtracts the voltages of the N bus from that of the NS bus. The result voltage includes the difference of the Vref voltage of each bus, ideally zero volts, and the image information for that pixel. This is a RZ (return to zero) type of signal;
(j) A correlated double sampler circuit (CDS) samples the subtracted signal at two points: the reference level and the image level. The CDS then takes the difference of these two points and generates a NRZ (non return to zero) signal; and
(k) The CDS output is then used as the input for the rest of the image signal processing chain.
FIG. 1 illustrates the one image sensor circuit employed to read signals from pixel images. A differential amplifier is formed from 101 and 102. Amplifier 103 combines the differential signals VN 111 and VNS 112 for processing in the correlated double sampler (CDS) 104.
FIG. 2 illustrates an alternate image sensor circuit employing a single differential amplifier 201. Differential amplifier 201 combines signals VN 211 and VNS 212 for processing in the correlated double sampler (CDS) 204.
The noise and the power associated with this solution are:Wtotal=2Wbuf  (1)Ntotal=√{square root over (2)}Nbuf  (2)where: Wbuf is the power for one instance of the buffer circuit; Wtotal is the total power consumption; Nbuf is the noise of one instance of the buffer circuit; and Ntotal is the noise total after summing. The total power equals 2Wbuf because there are two buffers in the output channel. The output channel total noise Ntotal is √{square root over (2)}Nbuf because the output of the two buffers is subtracted in the next processing step.
These factors make the buffer design difficult. Note that generally the gain A for each buffer will not be exactly the same:
                              A          N                =                  A          +                                    Δ              ⁢                                                          ⁢              A                        2                                              (        3        )                                          A          NS                =                  A          -                                    Δ              ⁢                                                          ⁢              A                        2                                              (        4        )            where: ΔA is the difference in gain between the gain AN and ANS. This causes a gain error once the VN and VNS signals are subtracted:VS,output=ANVS−ANSVNS=(A−ΔA)VS,output+ΔAVN  (5)where: VS,input=VN−VNS; and ideally VS,output=AVS,input.
Matching two buffers introduces two errors. First, the differential gain decreases by ΔA. Second, the gain mismatch amplifies the pixel-reset voltage (VN). Note that the pixel reset is different for each pixel but does not vary over time. This thus renders as a fixed pattern on the actual image.
Although the gain decrease is not usually critical, the pixel reset voltage pattern can easily become close to a 1 mVrms signal across the image that is clearly visible when the noise floor is less than 10 mVrms, which is commonly the case.
The differential amplifier approach has its own difficulties. A complicated aspect of its design is that its common-mode input changes constantly. The common-mode input is defined as the average of its input voltages:
                              V          common                =                                            V              ip                        -                          V              in                                2                                    (        6        )            where: ip stands for input-positive; in stands for input-negative; Vin is connected to the pixel reset signal VN; and Vip is connected to the pixel signal VNS. VNS is always smaller than VN because the pixel output becomes lower for more light. The output waveform VNS−VN is always less than or equal to zero. The amplifier input also has two segments: the bus line reset period, when Vip=Vin thus Vcommon=0; and the signal read in, where Vip≠Vin thus Vcommon≠0.
Thus the input common mode changes for each pixel. Depending on the design this difference can be as much as 0.5 V switching at 40 MHz. This makes the design for high common mode rejection ratio (CMRR) very challenging because the CMRR needs to be over 60 dB to produce fixed pattern noise less than 0.1 mVrms. The common practice is to introduce common-mode regeneration in the first stage of the amplifier. However, adding stages to the amplifier makes the design for high frequency and low noise more difficult.
Although the line memory readout was presented first as a series of capacitor discharges over the N and NS buses, this is not the only common approach. CMOS image sensors that present analog readouts follow one of these approaches capacitor discharge known as passive line memory or a buffer at each image column known as active line memory.
FIG. 3A and FIG. 3B illustrate the output waveforms of the two-buffer design. Each figure illustrates a repetition of two stages. There is a first stage called the reference stage. In the reference stage the output takes a known voltage Vref1 301 for the pixel reset level of FIG. 3A and Vref2 303 for the pixel signal level of FIG. 3B. The second stage is called the signal stage. In the signal stage the output takes a value that represents the actual pixel signal.
The N buffer signal 302 contains the pixel offset level. Reference signal Vref is normally chosen to be close to the average level of VN. Thus N buffer signal 302 usually has a small amplitude less than 100 mV. The NS buffer signal 304 contains the pixel offset plus the light-dependent signal. For most CMOS image sensors brighter signals translates into lower voltages.
FIG. 3C illustrates how the light-dependent signal component is extracted from signal 302 and signal 304 by subtraction. Reference signal Vref is canceled out during this process. Reference signal Vref can be identified in 305 during a time frame dedicated to it.
FIG. 3D illustrates how Correlated Double Sampling can be used on signal 305 in order to remove the time frame devoted to the reference voltage. Signal 306 only contains light information.
FIG. 4 illustrates the capacitor discharge approach. Each pixel column includes a pair of switches 401, 402 through 408 and a pair of capacitors 411, 412 through 418. The N-output bus 410 drives N output 424 through amplifier 422. The NS-output bus 420 drives output NS output 425 through amplifier 423. The operation consists of sequential column readout where each capacitor discharges over N bus 410 or NS bus 420. Buses are reset before receiving the data in order to prevent data from adjacent columns from interfering.
The buffer version of this circuit adds a buffer after each column capacitor 411, 412 through 418. These buffers prevent charge sharing. Under charge sharing VN and VNS signals usually drop by 50% because after connecting the capacitors to the buses, the charge previously present in the capacitors and the parasitic capacitance of the buses will redistribute itself and effectively produce a mix of the Vref, VN and VNS levels. This redistribution depends on the ratio of the column capacitor to the bus parasitic capacitance. Most designs target 50% resulting in a 50% signal loss. Using buffers at each column decreases such signal losses below 1%.
The buffer version is similar to the capacitor discharge approach in that it consists of two devices per column and a reference voltage 426. Switches 421 connect reference voltage 426 to N bus 410 and NS bus 420 to reset during the reset period. These two approaches introduce the same difficult mismatching challenge for the N and NS buffers. The problem is to match two elements which decreases the differential gain and causes fixed pattern error in the image.